Arteris Inc

Overview

We are a leading provider of semiconductor system IP, including interconnect and other intellectual property, (collectively, System IP) technology. Our System IP technology manages the on-chip communications and IP block deployments in System-on-Chip (SoC) semiconductors and systems of chiplets. Our leading proprietary System IP solutions achieve this by connecting client IP blocks such as processors, memories, artificial intelligence/machine learning (AI/ML) accelerators, graphics subsystems, safety and security, and other input/output subsystems (I/Os) via multiple Network-on-Chips (NoCs) in order for our customers to experience faster SoC targeting, as well as, more efficient, and lower cost solutions. Growth for our solutions is being driven by growing SoC sophistication and associated complexity, now extending into disaggregation of SoCs into systems which implement the communication protocol aspects and partner with industry leading providers like Synopsys, Cadence, Alphawave and others to connect to their die to die interfaces. The addition of more processors, channels of memory access, machine learning sections, additional I/Os interface standards, and other subsystems within SoCs is driving the need for more advanced System IP, including NoC interconnect IP’s. The growth in the numbers of these connected on-chip subsystems places an increasing premium on the interconnect IP capability to move data inside complex SoCs. We believe this increase in SoC complexity has created a significant opportunity for sophisticated System IP solutions that incorporate NoC interconnect IP, SoC Integration Automation software (SIA) (formerly IP deployment software)and NoC interface IP (consisting of peripheral data transport IP and control plane networks connected to NoC interconnect IPs). Moreover, our technology can also provide more cost-effective solutions and reduce the risks of building and maintaining in-house NoC teams, which we believe has positively contributed to our market segment share growth.

Founded in 2003, we are among the pioneers in the development of NoC IP technology for on-chip communication that addresses the growing complexity, performance, and cost requirements of SoC semiconductors and as a result, we have emerged as a global leader. Over time, we have expanded and scaled our interconnect IP and other IP businesses to provide hardware, software, documentation, support, and training under a license fee and a royalty business model, to companies that design and produce semiconductors. In addition, we are also finding an increasing number of customers further down the supply chain, such as system-level companies and automotive original equipment manufacturers (OEMs). Our SoC integration automation capabilities were significantly enhanced by our acquisitions of Magillem in 2020 and Semifore in 2022, complementing our interconnect IP solutions by helping automate the customer configuration of its NoC IPs, the process of integrating and assembling all the customer’s IP blocks into SoC hardware, and ensuring correct hardware-software integration for software development. Products incorporating our IP are used to carry important data inside today’s complex SoCs across a broad range of applications including automotive, enterprise computing, communications, consumer electronics, and industrial markets. Our interconnect IP solutions can be found in multiple industry-standard designs supporting instruction set architectures such as x86, Arm, RISC-V, CEVA, Synopsys ARC, Cadence Tensilica and MIPS, as well as memory controllers, UCIe, BoW, and XSR controllers, I/O and a variety of IP subsystems, to enable customers to integrate such IP blocks with high levels of efficiency and performance. Our solutions enable customer innovation because they are configurable for each customer’s design flow and SoC development projects and have wide applicability for many types of SoCs. We estimate that our solutions have been incorporated into three and a half billion production SoCs since inception.

Traditional on-chip communication methods, including bus and crossbar interconnect IPs, are generally inadequate in handling modern semiconductor communications, and even more so for sophisticated applications or more complex designs. Technological advancements have led to increasingly complex SoCs that integrate numerous functions into a single semiconductor device. Massive amounts of wires, challenging timing closure, and routing congestion lead to greater die area and chip cost. Increased transistor density and design frequencies create higher power consumption leading to heat dissipation challenges and shorter battery life for electronic devices. These challenges have significantly complicated SoC innovation and contributed to the increasing adoption of System IP, across the growing number of customer design starts coupled with the expanding number of NoC IPs used in current SoC.

We leveraged our extensive technical expertise to develop configurable IP for a new method for on-chip communication, the NoC, that has emerged over the past couple of decades to address these critical semiconductor development challenges. We accomplished this by pioneering the use of proprietary networking techniques for on-chip communications to remove the inherent architectural limitations of traditional on-chip communications, thereby improving ease of integration, performance, silicon area, and power consumption. In doing so, we enable our customers to achieve their design goals faster, more efficiently, and at lower costs. In addition, our SIA solutions enable easier IP integration of our interconnect IPs – among other IP blocks that make up an SoC, across both hardware and software.

We work directly with our customers throughout the SoC development process and seek to develop long-term, sustainable relationships with them as our technology becomes embedded in their products. Increasingly, we are also seeing system companies and even their customers becoming directly involved in SoC and NoC specifications and design, further expanding our ability to partner in this growing market. We also leverage our long history in interconnect IP designs and are able to serve a broad range of applications and deliver application and customer-specific features to our customers. For example, we are a leader in the market of interconnect for advanced driver assistance systems (ADAS) SoCs, which we believe is a result of our quality, reliability, and innovative technology targeted at that business application, and longstanding collaboration with automotive semiconductor companies, Tier 1 suppliers, and car manufacturing OEMs.

We provide solutions for the global SoC market and believe that market growth will be driven by an increasing number of SoC designs and growing complexity, increasing average selling prices of interconnect IP and SIA, and the growing proliferation of the NoC interface IP market segment. More specifically, we believe our growth will be driven by technology trends requiring more sophisticated on-chip processing in the automotive, communications, enterprise computing, consumer electronics, and industrial markets. Also, the need for sophisticated system IP products is growing rapidly in order to address the requirements of smaller die size, multi-die systems, lower power consumption, and higher operation frequency, as well as management of critical net latency in a timely and cost-effective manner. As a result, we believe these trends have led to an increased economic benefit of in-licensing commercial semiconductor design IP, a trend that we expect to continue.

For the years ended December 31, 2023 and 2022, we generated $53.7 million and $50.4 million in revenue, $15.7 million and $6.8 million in cash flows used in operating activities, and $36.9 million and $27.4 million in net loss, respectively. We expect to incur further net losses in the short term as we invest in our business. As of December 31, 2023, we had Annual Contract Value (ACV), which we define for an individual customer agreement as the total fixed fees under the agreement divided by the number of years in the agreement term, of $50.9 million. ACV and trailing-twelve-months variable royalties and other revenue reached $56.1 million as of December 31, 2023. Since our inception, our interconnect IP solutions have been used in over 760 unique SoC Design Starts. In 2023, we added 23 net new Active Customers. We define Active Customers as customers who have entered into a license agreement with us that remains in effect.

Industry Background

Semiconductor complexity is increasing as the industry moves from integrated circuits (ICs) that process data to SoCs that make decisions, and now extends to systems. Historically, a chip’s complexity was much lower as processors were connected to memories with relatively few peripheral IP block functions. Once the industry moved to 40 nanometer (nm) and more advanced process geometries, it became possible to build more complex SoCs, such as mobile phone application processors, which contained many more IP blocks and consequently required more sophisticated on-chip communications. With the rise of machine learning algorithms and architectures, such as convolutional neural networks, and semiconductor process technologies reaching 3nm geometries, with roadmaps to go beyond these process technologies, it became possible to build complex decision-making SoCs for applications such as automated driving and enterprise computing data center acceleration. Integration of processors, accelerators, machine learning subsystems, sophisticated multi-channel memories, and an ever-larger number of interface standards have placed a premium on the ability to move data efficiently inside the SoC and between SoC chiplets. These trends further highlight the growing importance of interconnect IP in today’s SoCs.

Increasing chip design complexity leads to rising costs. The slowing of Moore’s law and the need for more functionality and performance has necessitated new architectural paradigms and accelerated the move to more advanced process nodes. This has resulted in the adoption of significantly more expensive and complex chip design methods and manufacturing processes, creating a substantial rise in semiconductor design costs. Costs continue trending upwards, as the design costs of an advanced SoC have risen five times from the 16nm technology node to the 5nm technology node, according to the Semiconductor Industry Association, and are now extending to 3nm technology and beyond. This has placed increasing importance on the cost efficiencies provided by System IP solutions.

Increasing SoC complexity leads to increasing System IP value. It is common for today’s SoC to contain multiple types of data traffic in the same design, with a hierarchy of NoCs connecting sub-systems and eventually the top-level of the design. In addition, the large number of IP blocks in complex SoCs means that more data traffic must be successfully managed. Data must be brought to each of these IP blocks at a time where such data is required—otherwise that IP block will be “starved” of data. As their size has grown, partially due to the incorporation of machine learning subsystems, SoCs are being split into chiplets, which are smaller pieces of silicon packaged together into one unit. Communication between chiplets adds complexity, which increases the value of interconnect IP. Another complexity factor is the increasing use of cache coherent traffic which makes multiple processors and/or accelerators look like a single hardware programming space to the application software, simplifying software development. Many complex SoCs now use cache coherent and non-coherent traffic in a single SoC, raising the volume and value of our System IP solutions.

Increasing SoC complexity puts pressure on IP block assembly and connectivity efforts. With potentially hundreds of IP blocks coming from a variety of vendors and internal development groups, SoC teams need to manage the IP supply chains with increasingly capable SoC integration automation. These teams and their electronic design software (EDA) groups also need to put in place increasingly capable SoC integration methodologies to improve SoC development success. These developments have driven the semiconductor industry to use SoC integration automation standards such as IEEE 1685 IP-XACT which are becoming increasingly sophisticated with each generation and require more sophisticated software to support them.

Increasing demand from emerging end markets and new market participants. New applications in markets such as automotive, enterprise computing, communications, consumer electronics, and industrial have increased the diversity and overall demand in the semiconductor market. These new applications, often including an increasing level of AI/ML technology, safety, or complex hardware-software integrations, have led to an increase in the number and complexity of SoC designs. Chips used for AI training and inference acceleration have increased in die size, further increasing design costs with new design complexities and performance requirements. Also, new market participants, such as electronic system companies, internet hyperscalers, and automotive OEMs, have begun internally developing their own chips. The increasing demand from current and new market entrants is increasing the need for System IP solutions.

Shift to third-party IP for cost benefits, product differentiation, and accelerated time to market. It is difficult, time-consuming and expensive to develop state-of-the-art SoC interconnect IP solutions. We believe this dynamic is accelerating the degree to which interconnect IP solutions are outsourced to commercial vendors. Commercial interconnect vendors, such as Arteris, have the potential to accelerate time-to-market because they engage with a greater variety of SoC applications and a greater variety of designs than the typical internal interconnect teams. Commercial vendors are also able to spread interconnect and SoC development costs across a greater number of projects than internal interconnect and design teams.

System IP Market

SoC-type semiconductors consist of pre-made IP blocks that are either licensed from third parties by semiconductor and electronics companies or developed in-house. These IP blocks must be assembled into SoCs as efficiently as possible to address semiconductor company and system OEM customer requirements. Many of these IP blocks, including processors and other functional blocks, such as machine learning and vision subsystems, perform processing functions and execute complex software stacks. These IP blocks can number in the hundreds on a single chip and generate and consume commands and data, as well as work together as a unit. As SoCs become more complex, there has emerged a class of silicon IP and software tools designed to assemble these IP blocks into a functioning SoC at target cost and performance. We call this the System IP market. The System IP market consists of interconnect IP, NoC interface IP and SIA solutions. According to Informa PLC (Omdia), the semiconductor market is set to grow from about$604 billion in 2022 to $734 billion in 2026. As SoC technology evolves, we believe that there is a significant opportunity for us to grow our value by introducing additional functionality for our customers to integrate their SoCs efficiently using our System IP solutions.

Omdia segments the aforementioned semiconductor and OEM markets into six industry segments: automotive, computing, consumer, industrial, wireless, and wired communication. Our market penetration spans all of these segments and customer adoption is most pronounced in the automotive, enterprise computing, consumer electronics, communications across wired and wireless, and industrial segments, driven by a higher rate of disruptive innovations. While the key focus is in the SoC design itself, we greatly benefit from the verticalization trend in which traditional OEMs increase the control of their design chain driving system requirements into semiconductor and IP companies, and often take on the semiconductor design themselves or with their semiconductor company suppliers. These trends of specialization and OEMs controlling their own destiny in light of supply chain disruptions are amplified by trends towards heterogeneous disaggregation of SoC design into multi-die systems and 3D-IC assembly. Overlaid over the industry vertical markets mentioned above, the differentiation of semiconductor IP and tools is increasingly determined by the ability to address horizontal market aspects that span across the industry verticals. For instance, we differentiate with our readiness for safety certification for mission-critical and automotive designs, our ability to address specific requirements posed by AI/ML designs in enterprise computing data centers, automotive autonomous driving, and consumer and industrial edge designs. Our support includes standard processor architectures and our experience with enabling our readiness to enable our customers to optimize their System IP for specific semiconductor manufacturing technologies (such as TSMC, Samsung and Intel foundries).

Automotive Applications

The automotive market is undergoing technology disruption with the advent of automated driving, electrification, electronic control unit consolidation and vehicle connectivity to the internet. Furthermore, cars are becoming increasingly connected to a large network of data centers, roadside and city infrastructures, andother vehicles, creating the “Internet of Cars.”

The automotive semiconductor industry that is expected to drive the “Internet of Cars” is in a period of rapid growth. Omdia estimates that the automotive SoC market will grow from nearly $7.0 billion in 2023 to over $13.1 billion in 2027, at a CAGR of over 17.1%.

As the electronically enabled car has continued togrow in sophistication and performance, complex SoCs must increasingly receive, process and communicate data, further requiring advanced interconnect IP solutions.

The different levels of automated driving are defined as “Level 1” to “Level 5” with “Level 1” being sophisticated cruise control and “Level 5” being fully automated without the need for human driving intervention. Informa Tech LLC estimates that over half of all light vehicles sold in 2027 will be equipped with ADAS systems considered “Level 2” and above. Behind this leap in ADAS deployments is the growth in the number of ADAS-related semiconductors. Omdia estimates that the annual volume shipments of ADAS semiconductors will double from 2023 to 2027.

Due to the complex requirements of electronically enabled vehicles and the high rate of innovation required to compete in the “Internet of Cars” revolution, industry players are designing SoCs tailored to their sophisticated software and applications. This will result in more complex automotive-targeted SoCs, which we expect will continue to grow demand for reliable, configurable, and proven interconnect technologies that accelerate a product’s time to market while reducing overall costs.

The “Internet of Cars” revolution is disrupting the automotive supply chain. New business models such as ride-sharing, transportation subscriptions and transportation as a service are being created. New potential entrants such as ride-sharing companies, large data center companies, and new automotive startups are changing the automotive business landscape, while increasing demand for more sophisticated transportation-targeted semiconductors and therefore System IP solutions. In addition, the traditional automotive supply chain is also restructuring, with semiconductor vendors, automotive “tier 1” suppliers and automotive OEMs competing to own and control the electronic architecture of these cars. To compete, companies at all levels of the automotive supply chain have started creating their own chips, thus increasing the number of SoCs in the automotive industry and increasing demand for interconnect IP solutions.

The move toward the Internet of Cars may be non-linear and take longer than anticipated but since hardware decisions are often made between six and seven years before deployment, we believe that over the next 20 to 30 years, the creation of the internet of cars represents one of the largest semiconductor opportunities available.

Enterprise Computing Applications

Large-scale cloud data centers are augmenting and replacing corporate data centers. This evolution expands the market size and value for enterprise solid-state storage systems and the custom ASICs that control them, further strengthening demand for interconnect technologies that improve storage performance and provide data integrity. In addition, enterprise hyperscale computing companies are now creating proprietary SoCs and accelerators for their own products and data centers. We believe that these new entrants into semiconductor design will increasingly provide market opportunities for third-party System IP solutions, including those from Arteris.

Some of the key areas for workload specific acceleration in data centers are in AI/ML, database processing, video/audio transcoding, and scientific computing. AI/ML SoCs must be “trained” on large data sets that have to be collected from real-world data utilizing “training” SoCs. A different class of AI/ML SoCs uses such data to match the training data against actual data collected by sensors of the system utilizing “inference” SoCs. In 2023, Gartner estimated that the market for such AI-enabled applications processors will nearly triple from 2022 to 2027. AI/ML is deployed in cloud data centers for applications such as personalized advertising and credit card fraud detection. AI/ML is also deployed at the edge of networks for applications such as automated driving, cell phones and numerous other applications, and is as such considered a technology addressing various industry vertical business segments.

Communications Applications

The wireless communications market is in the midst of disruption as it allows efficient machine-to-machine communications at a massive scope and scale. 5G technology allows the cost-efficient connections of massive numbers of embedded sensors and other devices into ultra-reliable, high-bandwidth, and low-latency networks. In short, 5G enables smart devices utilizing sophisticated SoCs to communicate more information at faster speeds while using less power. As 5G is adopted as the wireless market standard, it is expected to revolutionize markets, including cars and smart city vehicle infrastructure, factory automation, logistics, and consumer and business broadband. For example, Ericsson estimated that there will be 9.2 billion global mobile endpoints by 2028, with mobile traffic up to 21 exabytes per month, up from 6 exabytes in 2022. Further, in February 2023, Ericsson forecasted that 5G will make up a growing part of this traffic, with 5G subscriptions growing from 1 billion subscribers in 2022 to nearly 5 billion in 2028. Already approaching the next generation network infrastructure, the industry has started the development of a roadmap towards 6G technology to be rolled out towards the end of this decade, with various 5G Advanced steps in-between.

We believe the transition to 5G and 6G will accelerate System IP market growth because the high complexity of 5G and 6G chips require more stringent requirements for bandwidth, latency, and power consumption, making an easy-to-integrate, high performance and low power on-chip interconnect a critical requirement.

Other Applications and Technologies

The consumer electronics and industrial markets are also expected to require increasingly complex chips primarily driven by the incorporation of AI/ML processing, particularly at the edge, increased use of 5G communications, and more stringent safety and security requirements. In addition, the chip market in these domains are sensitive to time-to-market pressures, which also generates the need for increased semiconductor design productivity and faster implementation as enhanced by sophisticated interconnect IP solutions. Our low-power features are valuable for battery life and power consumption in our targeted markets.

AI/ML semiconductor structures require multiple IP blocks that use peer-to-peeron-chip communications that have different data traffic characteristics than other parts of the SoC and thus require special interconnect features. Such interconnect features require greater attention to challenges including deadlock avoidance and mesh performance and the ability to transfer large amounts of data to memories.

Besides the AI/ML technology that is especially pronounced in high-performance enterprise computing and automotive application, as well as at the edge that enter the industrial, consumer electronics, and communications applications, functional safety is a key technology horizontal driving our differentiation and growth. We enable our customers to achieve ASIL-B and ASIL-D ISO 26262 certification with our products addressing the NoC Interconnect IP NoC Interface IP markets. Further, critical tools in our SIA product portfolio have been “Tool Confidence Level” (TCL)-certified by the TUV SUD to confirm that they are safe to use in automotive and mission-critical markets like aerospace & space as part of the industrial vertical.

Both our NoC Interconnect IP and NoC Interface IP are used alongside processor architecture and eventually mapped into semiconductor manufacturing technologies. Key processor architectures of note are the x86, Arm, and increasingly RISC-V processor architectures. We have entered into agreements with Arm in 2022 for automotive electronics and are an integral part of the RISC-V ecosystem providing the core interconnect IP for the growing number of SoCs deploying that processor architecture. Besides its safety aspects, we believe our NoC interconnect IP technology is differentiated through its ability to optimize designs for the physical layout, therefore believe we are part of the ecosystem of Cadence, Synopsys, Siemens EDA, as well as semiconductor manufacturing including TSMC, Samsung Foundry, GlobalFoundries, and Intel Foundry Services.

Industry Challenges

Interconnect IP development is a challenging, time-consuming, and expensive process. The need for robust, maintainable interconnect technology becomes increasingly important as chip designs become more complex and larger in size, both driven by advances in semiconductor manufacturing technology. As semiconductor manufacturing technology has advanced, it has increased the number of IP block functions that can be added to SoC type semiconductors. However, as more IP block functions are added to a chip, the sheer number of physical connections required for communications between the on-chip IP blocks grows massively. Therefore, the larger and more complex the SoC, the more important the on-chip interconnect for overall chip performance, power consumption and cost. Interconnect and SoC integration automation technology is key to allowing SoC designers to design these types of chips while meeting their technical and time-to-market requirements. The industry is challenged to meet these requirements by itself because of the technical know-how to do so. Further, any failures due to quality issues are enormously expensive and industry standards for mission-critical applications like automotive are costly to meet. All these technology trends combine to require a large initial investment and a long-time commitment for a chip design team or commercial interconnect IP company to create semiconductor IP and software technologies that satisfy industry needs.

■Deep technical expertise and knowledge. Interconnect development requires an interdisciplinary engineering team with expertise and skill sets across a wide-range of engineering and scientific domains including hardware architecture, design, verification, EDA-class software development, and SystemC modeling, as well as deep understanding of physical design, design methodologies and networking architectures. The design process requires expertise in developing advanced hardware architectures to handle data coherency and consistency across the interconnect to achieve a high-performance, low power implementation. Complex flows and methodologies as well as specialized languages to generate configurable hardware and interconnect configuration software must also be designed, with hardware configurations defined using thousands of parameters that need to be meticulously managed, with millions of combinations to be considered. The interconnect design process also requires engineers to have an awareness of the physical implementation and floorplan of the target chip to generate an architecture that meets SoC requirements in terms of timing, area, and power. Designers require an in-depth knowledge of graph theory, common interface protocols, data models, and graphical user interfaces. In addition, they require the skills to develop design methodologies to manage dependencies in project execution where the interconnect configuration software generates the hardware IP and associated data evidence of product quality and compliance with industry standards.

■High quality. Interconnect IP requires a systematic deployment of quality-oriented methodologies, as any customer-level problems in the interconnect will result in SoC project delays or even project failures. Engineering teams creating interconnects must invest heavily not only in skilled engineering resources to develop and verify, but also processes and methodologies that provide early indication of any potential quality issues. The best interconnect engineering teams also leverage these methodologies to help automate design and verification tasks, which helps improve time to market for the interconnect IP provider. If the interconnect has serious problems, the SoC will not be operational, resulting in significant economic losses.

■Safety standards. High reliability of the interconnect is a heightened requirement for mission-critical markets including automotive, industrial robotics, medical and space. An in-depth knowledge of and adherence to standards, such as the ISO 26262 automotive functional safety standards, further increases the challenge of developing a reliable interconnect targeted at these applications.

■Long time commitment and high investment cost. We believe the engineering development cycle for each new interconnect and the market development cycle to establish a significant market position for a customer or for a commercial vendor requires large teams, many years and great expense. Additionally, we believe the investment required by a customer to internally create a configurable interconnect technology for a new SoC can be very expensive compared to the cost of licensing from a proven interconnect IP provider.

■Breadth of System IP solutions. With needs to address cache coherent, non-coherent, machine learning and chiplet traffic, customers need a System IP solution that works together across all these data traffic types. SoC integration automation technologies allow customers to manage the deployment of the rest of the IP blocks in the SoC in order to ease SoC IP integration. Meeting such requirements requires significant enterprise scale in engineering and customer support. Necessity for such combined technologies amounts to a significant barrier to entry in terms of time, cost and customer adoption.

Given the above requirements and challenges, developing commercial interconnect IP and software tools require large engineering teams with advanced skill sets, significant amounts of time, and substantial financial investment. By licensing commercial interconnect IP, companies can free up resources to focus on developing new product capabilities and differentiators. Further, we believe the large investments needed to develop commercial interconnect IP also create barriers to entry for potential commercial competitors.

Our Solutions and Competitive Strengths

We are a leading provider of interconnect and other IP technology that manages the on-chip communications in SoC semiconductor devices. We believe our System IP is integral to our customers in the automotive, enterprise computing, consumer electronics, communications across wired and wireless, and industrial markets. Our core strengths include:

■We help accelerate our customers’ time to market. Our interconnect IP software and SIA solutions help accelerate SoC development at several different steps in the design cycle. For example, we offer design exploration and modeling capability for SoC architects to explore the interconnect IP performance of their designs ahead of hardware description language generation to speed up SoC architecture definition. As another example, we have automated test bench generation to accelerate the verification of our interconnect IP products. Still further, our physical awareness capability allows the estimation of critical net latencies and estimates whether the interconnect IP will meet our customers’ required timing. Our System IP product lines are structured so that our customers can customize the interconnect for their needs, helping accelerate interconnect IP customization for their particular SoC configurations. In addition to interconnect IP productivity features, we offer a combination of automated interconnect configuration software, pre-verified interfaces to IP block protocols, pre-verified interfaces to EDA tools and a pre-verified interconnect IP element library for rapid generation of customer-specific interconnect IP products. Our SIA solutions also help accelerate SoC development by enabling the IP blocks making up an SoC to be packaged in a standard format called IP-XACT (Institute of Electrical and Electronics Engineers—IEEE 1685), which provides a uniform IP block assembly and reuse methodology. Our SIA tool suite includes numerous packages that allow the configuration of IP block exit port registers, establish high-level SoC connectivity and link documentation to the IP-XACT design information.

■Our products help improve the performance of our customers’ SoCs. We believe that using our System IP solutions can result in improved SoC metrics such as higher performance, lower power consumption and smaller die area. We have extensive low-power management features such as three levels of clock gating and power domain features for low-power applications such as smartphone application processors and other SoCs for hand-held applications. We enable customers to partition their designs into “frequency domains”, allowing some domains to run at higher frequencies than others, in order to trade off performance against SoC power consumption.

■We enable lower customer research and development and SoC unit costs. We believe that we enable lower chip research and development costs, lower SoC unit costs and reduce project risk as compared to solutions developed internally or licensed from another vendor. We have targeted our interconnect IP to be area-efficient so that we can offer silicon area savings, and resulting chip cost savings, compared to other interconnect IP alternatives. For example, the interconnect IP generally makes up a meaningful proportion of the overall SoC area at the completed SoC stage, and savings of 1 square millimeter of area can potentially offer significant savings in terms of SoC unit costs. We provide an integrated package of software, hardware, documentation, verification tools and pre-verified interfaces to major IP blocks and EDA tools. We believe our IP and software can save our customers time and money and enable them to focus on product differentiation and revenue generation.

■We believe we have grown our product portfolio through robust and focused research and development. Developing commercial interconnect IP and software tooling requires large and specialized engineering teams, significant amounts of time and extensive periods of commercial productization. We believe we have been the pioneer of using networking technology for on-chip communications and have been licensing such interconnect IP products since 2006. Our strategy is to deliver at least one new Interconnect IP or SIA product release per year, and we have done so since 2013. As of December 31, 2023, we have 145 development engineers on staff covering IP hardware, software, verification, testing and methodology development. Such a sizeable, multi-disciplinary engineering team allows us to undertake System IP products of sizeable scale and permits us to work on multiple product development projects at the same time.

■We have grown our solutions through targeted acquisitions. We intend to continue to support a robust internal technology development program that is complemented by synergistic acquisitions to increase customer productivity and to lower SoC development and production costs. We believe we have the ability to complement our product development with selective acquisitions to strengthen our System IP product portfolio. With our acquisition of Magillem in 2020 and Semifore in 2022, we added complementary technology that helps automate process of integrating and assembling all the customers’ IP blocks into an SoC, and its hardware-software integration to accelerate end product system development.

■We are able to address mission critical applications. We believe we are positioned to take advantage of the rapid growth of semiconductor content in cars. We have been focused on the automotive market segment since inception and have 140 automotive SoC design wins. Additionally, we have established customer relationships with market leaders such as Mobileye/Intel, BMW, NXP, Bosch, and Dreamchip. In addition to ADAS and autonomous driving control systems, our interconnect IP is used in radar, lidar, vision, communications, and dashboard/driver management. As cars continue to grow in complexity and connectivity, we believe there will be significant growth in the number of increasingly powerful SoCs that will need automotive grade on-chip interconnect IP. Our interconnect IP is designed to meet the automotive safety integrity level D (ASIL D) of the ISO 26262 automotive functional safety standard, which is the highest level, helping to position us as an ideal partner to innovative companies in the advanced automotive SoC market. We believe our solutions make it easier for our automotive semiconductor “tier 1” and OEM customers to collaborate and meet functional safety standards by establishing traceability between requirements, specifications, hardware and software implementation, verification and testing, and quality assurance. Because of this, our SIA solutions are a complement to our interconnect IP in helping our customers meet their ISO 26262 functional safety requirements. Recently, our System IP and its resilience features have also seen increasing adoption for space exploration related applications.

■We have developed a “Connected by Arteris” ecosystem to provide a broad set of System IP solutions. Interconnect IP is the data transport backbone of the SoC, connecting IP blocks such as CPUs, GPUs and memory controllers. We work with suppliers who provide these blocks, including IP companies such as Arm, SiFive, MIPS, Synopsys, Cadence Design Systems, Semidynamics, Andes, Codasip and other RISC-V IP vendors to support their products and protocols working with our SIA and interconnect IP products. By offering an unbiased, standards-based interconnect infrastructure to which other IP vendors can connect, and supporting a broad range of transaction protocols, we believe we have simplified the industry’s development of heterogeneous SoCs while solidifying our role as a neutral, technology-agnostic provider across the semiconductor industry. In addition to on-chip integrations with partners, we work with EDA companies such as Synopsys, Cadence and Siemens to provide prepackaged interfaces to their EDA tools such as simulators, modeling systems, and logic and physical synthesis tools. By working closely with semiconductor IP and EDA leaders, some of whom compete with each other, we believe we have established credibility as a trusted enabler to integration of their products within our joint customers’ chips and design flows.

■We believe we benefit from distinct competitive advantages. We believe our interconnect IP technology benefits from barriers to entry due to our many years of experience and the strength of our proprietary solutions, as well as the significant technical expertise and research costs required to develop a competitive product. We were founded in 2003 when we believe we helped pioneer the industry’s NoC interconnect IP and have maintained our competitive position with our global team of 145 hardware and software engineers as of December 31, 2023. Developing interconnect IP requires an interdisciplinary engineering team with expertise and skill sets across a wide range of sciences and domains as well as a deep understanding of semiconductor physical design, design methodologies, and networking architectures. Building such teams and keeping them together over long periods of time presents a challenge for many companies and we believe it provides a competitive advantage to us. Additionally, strategic patience and focus are required to participate in the market. For example, we believe that the customer acquisition process has a typical duration of two to nine months; following this, a customer’s chip design cycle is typically between one to three years. Customers typically start shipping their products containing our interconnect IP solutions between one to five years following completion of their product design, known as mass production at which point we start to receive royalties; this lasts for up to seven years or longer depending on the market segment. We also leverage our long history of interconnect IP design to deliver customer-specific features, further deepening our relationship and integration with the customer’s product. We are able to market such features to the rest of our customer base, sharing the benefits of our research and development with them. With our System IP products embedded in our customers’ SoCs, there are significant switching costs in moving to alternative solutions. We believe that our product quality and technical strength have enabled our high customer retention rate.

■We offer global support for our System IP customers. Interconnect IP technology is complex, and our customer support is critical for the successful deployment of our IP in our customers’ designs. We support customers utilizing our interconnect IP solutions on a global basis with architectural reviews, training, implementation support, and tape-out support. We work directly with our customers throughout their design processes to develop long-term sustainable relationships as our technology becomes embedded in their products. We have 38 corporate and field application engineers in our global support organization. Many of our application engineers have advanced degrees, years of SoC design experience and passion for helping our customers drive their SoC designs to production status. We believe our application engineers are critical advisors to our customers’ design teams and offer competitive value to our customer’s SoC creation projects.

Our Growth Strategy

We believe that as SoCs become more numerous and complex, the value of System IP technology increases since it enables the efficient movement of data within the ever-growing number SoCs. We also believe that, as SoCs become more complex, interconnect IP technology becomes more time-consuming and riskier to develop internally within semiconductor and system companies, favoring System IP solutions provided by outside parties such as Arteris. As a dedicated interconnect IP provider, we enable our customers to leverage the knowledge and deep expertise developed by us through many years of focus on solutions for a variety of customers.

Our growth strategy includes the following:

■Leverage our System IP technology leadership and focused research and development to provide solutions for the semiconductor industry that designs and builds complex SoCs. We devote the majority of our operating expenses to research and development of interconnect IP and SIA-related solutions and technologies to retain our System IP market position. We believe that the semiconductor industry needs an independent interconnect IP infrastructure that various IP block companies can connect to without competitive bias. We intend to remain neutral regarding the connection and integration of SoC IP blocks whether they are sourced from IP block vendors or are internally developed. We intend to continue to compete vigorously in the interconnect IP segment and to support and minimize the risks of competing with, our valued partners and customers developing non-interconnect IPs. We intend to remain focused on providing interconnect IP and software technologies for the semiconductor industry and system companies that build SoCs.

■Address high-growth segments such asautomotive, enterprise computing, consumer electronics, communications across wired and wireless, and industrial segments. We are focused on fast-growing semiconductor market segments. We have been focused on the automotive market segment since 2012 and have over 130 design wins in this sector. We intend to continue providing regular introductions of interconnect IP products to enable the semiconductors that are connecting cars, roads, and the cloud resulting in the “Internet of Cars.” We are also focused on the emerging edge and wireless communications markets, which are particularly sensitive to power consumption and idle power, and we believe these market segments can continue to benefit greatly from our low-power interconnect IP solutions. In addition, we are targeting emerging AI/ML-enabled applications that leverage massively multi-core architectures. As of December 31, 2023, we had 123 customers who have built or are building advanced AI/ML-enabled applications, which accounted for 205 of our customers’ Design Starts. We intend to maintain our focus on automotive, enterprise computing, and consumer electronics, as well on technologies such as Safety, AI/ML and others, while expanding further within communications and industrial markets.

■Expand our customer base through ongoing System IP innovation. SoC evolution has continued at a rapid pace and with it the demand for System IP solutions. New technologies and trends driving the need for System IP development include innovations such as cache coherency outside of the processor subsystem, machine learning SoCs utilizing peer-to-peer data traffic, greater use of separate sets of dies, or chiplets, inside SoCs, and the increasing emphasis on silicon functionality and safety. We believe that the complexity of these trends necessitates ever-increasing sophisticated System IP solutions and represents a great opportunity for Arteris as a leading commercial company focused exclusively on these solutions. Our goal is to deliver interconnect IP technology and deployment solutions ahead of when the SoC industry requires them. We aim to deliver at least one new interconnect IP or SIA product every year, addressing new SoC technology needs. We intend to expand the functionality of interconnect by adding NoC interface IP products that leverage SoC data moving through our interconnect IP products. Such NoC interface IP products may include a variety of types of inter-chip links for seamless connectivity, which make up larger system-in-package type SoCs and memory schedulers. These offer end-to-end quality of service (QoS) and error correction code (ECC) as well as a variety of new last-level cache memory products giving our customers the choice to either keep data on-chip or move it to off-chip dynamic random-access memory (DRAM). We believe such roadmap products can expand our market and offer an opportunity for us to further expand the value of our System IP products. In addition, we plan to continue to work with customers to deliver product enhancement releases for existing products. These requirements are identified in part by our global sales and application engineering organization that is engaged in helping customers utilize our products and solutions.

■Expand our customer base through increased investment in sales and marketing. We plan to continue to expand our global sales and application engineering organization, which has a strong presence in North America, Europe, the Middle East, China, South Korea, Japan, and India. We hire local talent who are attuned to the key regional needs of local markets, customers and languages. While most of our customer engagements are handled directly by our regional sales and application engineering forces, we utilize distributors in Israel and India for interconnect IP, although this represented less than 5% of our worldwide revenue in each 2023 and 2022. Our marketing is focused on helping customers understand the value of our solutions and creating awareness of the latest developments in our markets. We believe a key measure of our success is the number of successful SoCs produced by our customers utilizing our technology. To date, there have been over 380 production SoCs designed with our technology. We estimate that our solutions have been incorporated into three and a half billion production SoCs since inception.

■Continue to pursue selective acquisitions and other strategic transactions, such as joint ventures, to acquire complementary solutions and accelerate growth. We intend to continue to target acquisitions to achieve our objective of making our System IP solutions critical to the next generation of SoC design and development. For example, we acquired the assets of Magillem in 2020 and Semifore in 2022 to deliver synergy between the network-on-chip IP and tooling for IP packaging, SoC assembly, and hardware-software integration for software development teams. With these acquisitions, we added complementary technology to our portfolio that helps automate customer configuration, integration, and assembly of the interconnect into an SoC. In addition, these SIA tools allow us to gain a deep understanding of the entire “bill of materials” of the IP blocks integrated into an SoC, as the interconnect IP is the on-chip means to connect these blocks. We believe our planned continued integration of these technologies can provide substantially increased efficiency in the effective development of SoCs. In addition, we anticipate this integration can lead to added benefits such as automated documentation, traceability for quality processes and functional safety, and software driver optimization to reduce defects, providing significant customer value. For example, we invested in Transchip, a joint venture in China in the second quarter of 2022. In exchange for providing Transchip with a non-exclusive license (without standalone resale rights) to utilize substantially all of our interconnect IP products and SIA solutions, we retained a minority, non-controlling interest in Transchip. The other investors in this joint venture are principally Chinese-based venture capital entities and include one of our investors that holds less than 5% of our outstanding common stock and contributed cash.

NoC Interface IP Growth Opportunity

NoC IP carries the majority of the data in an SoC. As a result, there is an opportunity to add additional customer value by developing additional data plane and control plane capabilities that attach directly to our interconnect IPs and are implemented in SoCs by our IP software. Currently, we offer NoC interface IP products such as a memory scheduler, last-level cache, SoC data visibility and SoC debug IPs. We see an opportunity to further expand our product portfolio and market with additional control networks and subsystems that can accelerate our customers’ ability to deliver production SoCs to their end markets. Such networks may include clocking, register management and interrupt networks. Control subsystems such as power management, security, performance monitoring and debug may provide additional value to customers looking to lower the cost and risk of SoC development. With the integration of interconnect IP and NoC interface IPs, we believe we would be able to provide end-to-end solutions for quality of service, system level security and SoC resilience. NoC interface IP represents a natural expansion of our technical and business capabilities.

Our Solutions

We provide semiconductor interconnect IP and SIA solutions to serve our target end-markets, including automotive, enterprise computing, consumer electronics, communications across wired and wireless, and industrial segments. We regularly release new products to address the rapid evolution of SoC technology, across our two core product platforms:

a. Network-on-Chip IP Products

i. Non-coherent NoC IP, with FlexNoC and FlexWay

ii. Cache-coherent NoC IP, with Ncore

iii. Last-level cache, with CodaCache

b. SIA Solutions Products

i. IP and SoC software, with Magillem and CSRCompiler

In addition to historical annual introductions of new System IP solutions, we regularly develop and deliver updates that provide product enhancements to our customers. We believe the combination of our solutions and the strategic neutrality that we offer to the semiconductor industry positions us well as a reliable, trusted and innovative System IP solution for our customers.

Network-on-Chip IP Products

We believe we offer the semiconductor industry an industry-leading commercially available interconnect IP portfolio.

Our commercially available interconnect IP products are shipping in billions of devices worldwide. Innovative use of proprietary networking techniques for on-chip communications has enabled our industry-proven solutions to deliver higher SoC performance with shorter design schedules, lower research, and development costs, lower SoC unit costs, and reduced project risk when compared to customer-developed internal solutions. Select offerings of our semiconductor IP product portfolio include:

■FlexNoC and FlexWay: Silicon-proven, interconnect IP products that have been integrated into hundreds of chip designs. The underlying NoC technology converts on-chip communication signals between IP blocks, such as reads from and writes to memory, into digital packets. Packetizing on-chip communications allow the interconnect to be configured for enhanced performance and simplifies the connections of on-chip IP blocks, similar to how the internet eases the simultaneous connectivity of large numbers of computing devices. FlexWay is targeted at simpler SoC while FlexNoC targets the mainstream application. We also provide optional add-on packages for FlexNoC and FlexWay, such as the resilience package, which provide on-chip data protection that enables customers to meet the ISO 26262 and IEC functional safety standards for markets like automotive, and a large design performance package that addresses highly scalable peer-to-peer on-chip communications required by large SoCs such as those which include machine learning neural networks. FlexNoC and FlexWay started shipping in 2011 and we estimate that our solutions have been incorporated into three and a half billion production SoCs since inception.

■Ncore: Silicon-proven, cache coherent interconnect IP product that provides scalable, configurable, and area-efficient features for use across multiple end markets. In an SoC, cache coherency is a special data traffic class that requires a corresponding coherent interconnect IP to manage it. In a multiprocessor system using shared memory, each processor has a local cache memory for efficiency, however, it is possible to end up with many copies of shared data in the system. One copy of the data may be in the main memory, whilst other copies may exist in one or more of the processor cache memories. When one of the copies of data is changed, the rest must also reflect that change. Ncore assists the timely propagation of data changes across the SoC in order to maintain cache coherency. Ncore is also more scalable and area-efficient than mesh-based interconnects and is optimized for heterogeneous cache coherent systems and offers multiple configurable snoop filters, multiple configurable proxy caches, and a modular, distributed architecture to provide system architects with the most advanced technology and more degrees of freedom to innovate. Since the initial shipment in 2016, we have launched multiple releases of Ncore which have been designed into various production SoCs for automotive, consumer electronics, industrial, and communications applications. In 2022 we also entered into an Arm automotive agreement, with Arm as the processor IP provider and Arteris as interconnect IP provider for automotive microcontrollers (MCU) and SoCs to service growing customer needs. In 2023 Ncore achieved ISO 26262 certification up to ASIL-D, the most stringent level of functional automotive safety.

■CodaCache: CodaCache is a silicon-proven, last-level cache (or local memory) semiconductor IP product, used anywhere in the network-on-chip, for minimization of SoC data latency or improvement of performance. Frequent DRAM accesses waste clock cycles and causes performance to drop. CodaCache keeps data closer to the access point and lowers costs in certain SoC architectures. Design teams and architects can easily configure CodaCache based on area, timing, and other requirements. CodaCache provides the most flexibility of any commercial on-chip last-level cache IP, from setting associativity up to 16 ways, to configuring cache sizes and multiple target ports.

SIA Solutions

We provide a suite of SIA solutions that enables the packaging, reuse and integration of most types of IP blocks using the IP-XACT (IEEE 1685) standard. This SIA suite of products from Magillem and Semifore acquisitions provides a design environment to any semiconductor and system company from the architecture of the SoC through the delivery of a fully documented and traceable chip design. This software suite manages the assembly of multiple IP blocks into SoC devices, registers configurations of IP blocks, and links design parameters and metadata to documentation. Our SIA solutions are designed to shorten our customers’ design schedules and improve SoC engineers’ productivity across architects, logic designers, software/firmware developers, verification teams, and documentation teams. Arteris products provide a broad suite of software front-end design capabilities that can accelerate SoC development by providing highly configurable and scalable solutions. Our solutions address packaging, connectivity, register configuration, embedded software, and design software flows and we believe we provide best-in-class front-end design environments based on worldwide IEEE 1685 IP-XACT extensible markup language (XML) standard and SystemRDL language through our ready-made design solutions.

We believe the combination of SIA solutions and SoC interconnect hardware provides our customers with more comprehensive SoC integration capabilities. Our SIA technology suite across Magillem and CSRCompiler products cover the following key capabilities for SoC integration automation and overall SoC development acceleration:

■Magillem Connectivity: The Magillem connectivity product shortens and streamlines the system-on-chip (SoC) integration process. Magillem Connectivity allows users to build very complex, correct-by-construction SoC designs. IPs are packaged by the tool using the widely supported IP-XACT standard and can be configured and instantiated to create an SoC design in a single environment whilst ensuring design-data consistency. Magillem Connectivity uses built-in checkers to help automate time-consuming tasks, resulting in efficient and safe design updates or even restructuring of large sections of the design.

■Magillem Registers and CSRCompiler: The combination of Magillem and CSRCompiler products addresses hardware-software integration challenges for SoCs, where complex software algorithms control a growing array of specialized processors and hardware accelerators to deliver a robust semiconductor. The hardware/software interface (HSI) provides the technology for software to control this SoC hardware and it forms the foundation of the entire SoC design project. The Magillem Register product and CSRCompiler products automate the creation of this SoC foundation.

As mentioned above, critical tools in our SIA product portfolio have been “Tool Confidence Level” (TCL)-certified by the TUV Sud to confirm that they are safe to use in automotive and mission-critical markets like aerospace & space as part of the industrial vertical.

Customers

We license our products to a global and diverse customer base, including semiconductor manufacturers, OEMs, hyperscale system houses, semiconductor design houses and other producers of electronic systems. We work directly with our customers throughout their design processes and seek to develop long-term, sustainable relationships with them as our technology becomes embedded in their products. As a result, we believe we are well positioned to continue to attract and retain customers, and to continue developing next-generation System IP solutions for their future products. We added 23 net new Active Customers during the year ended December 31, 2023.

In 2023, we had one customer that represented more than 10% of our revenue. Our key customers include Intel, Samsung, NXP, STMicroelectronics, and Socionext.

During the fiscal year 2023, our net new Active Customers were geographically distributed as follows:

■8 net new Active Customers based in the Americas;

■2 net new Active Customers based in Europe and the Middle East; and

■13 net new Active Customers based in the Asia Pacific region.

During the fiscal year 2023, our revenue by geographic area based on customer location was as follows:

■35.9% of our revenue was derived from customers based in the Americas;

■12.0% of our revenue was derived from customers based in Europe and the Middle East; and

■52.1% of our revenue was derived from customers based in the Asia Pacific region.

Sales and Marketing

We work closely with our customers throughout the SoC design lifecycle to help them use our System IP solutions to meet their specific needs. It is important to our success that we engage our customers early and collaborate throughout the design cycle. Our support organization is able to communicate the best practices in SoC design practices and receive early insight into customer requirements. This insight often results in new and innovative product features.

System IP sales cycles range from two to nine months or longer. For repeat customers, our sales cycle length is generally shorter.

As of December 31, 2023, we maintained sales offices, sales personnel, or sales representatives in the United States, China, France, South Korea, Japan, and Israel. As of December 31, 2023, our sales management had an average of 25 years of sales experience. As of December 31, 2023, we had 38 corporate and field application engineers. Corporate and field application engineers work closely with our customers in both presales and support roles, providing expert advice to our SoC architect and engineering users on how best to use our IP and software to design and implement their SoCs. As a result of these close relationships and detailed information sharing, our application engineers gather early knowledge of future expected customer needs including potential new sales opportunities within the customer and requirements for new capabilities for our products. Therefore, we believe our close relationships and technical credibility with our customers provide a competitive advantage.

Our marketing strategy emphasizes thought leadership and educates potential customers about how our products can address their System IP challenges. We use technical papers, and in-person and online events, to highlight our capabilities.

Research and Development

We devote the most of our operating expenses to research and development of interconnect IP and SIA solutions. The development of interconnect IPs for complex SoCs is a challenging task that requires multiple competencies and close contact with customers in order to deliver sophisticated solutions. The development and maintenance of these solutions require:

■Management of an interdisciplinary engineering team with expertise and skill set across a wide range of sciences and domains such as architecture, design, design verification, EDA-class software development, and SystemC modeling, as well as deep understanding of physical design, design methodologies and networking architectures;

■Advanced SoC architectures for handling data coherency and consistency that result in a high-performance implementation with low power;

■Complex design flows and methodologies, as well as specialized languages for generating configurable interconnect IP. The designs require configuration using thousands of parameters that must be meticulously managed with millions of combinations;

■Capability to understand the physical implementation and floorplan of the target SoC in order to generate a design that meets physical implementation requirements in terms of timing, area and power;

■Sophisticated design verification methodologies to ensure the quality of configurable interconnect IP across millions of possible combinations, as well as complex test benches for simulation and emulation;

■In-depth knowledge of common interface protocols, graph theory, data models and graphical user interfaces;

■In-depth knowledge of safety standards including ISO 26262 ASIL B/D for automotive, IEEE 1685 IP-XACT IP standard for IP and SoC packaging, IEEE 1800 UVM verification standard; and

■Support a broad ecosystem of processors suppliers, other IP vendors, SoC design tool software providers, semiconductor foundries, and others.

SoC integration automation development is similarly challenging as it requires broad support of the IP packaging standard, IEEE 1685 IP-XACT, and the ability to deliver features and enhancements required as customers deploy ever-changing IP block libraries for their SoC projects, address hardware-software integrations. Our SIA solutions have to conform not only to industry standards, but also to ever-evolving SoC integration methodologies.

Once interconnect IP is designed into customer SoC projects, there are significant switching costs to adopting different interconnect IP and SIA solutions, especially in the automotive sector where switching interconnect IP solutions may involve product functional safety re-certification.

Our research and development strategy includes offering customers several product enhancement releases per year, complemented with a planned introduction of at least one new interconnect IP or SIA product every year.

We believe we have assembled one of the premier engineering teams for interconnect IP development and SIA in the world. As of December 31, 2023, we had 89 engineers devoted to interconnect IP development and 56 engineers devoted to SIA solutions totaling 145 employees. In 2023, we spent $45.1 million on research and development, which represented 84% of our revenue.

Competition

For interconnect IP, we primarily compete with interconnect solutions developed internally by our SoC customers and potential customers. Many of the largest semiconductor companies have their own interconnect IP development teams which make customer penetration relatively difficult, time-consuming, and expensive. However, we believe that over time the expense and difficulty of developing a broad suite of interconnect IP and SoC integration automation has the potential to expand the use of commercial SoC integration solutions. In addition, we also compete with third-party providers, including Arm and several smaller companies. While we do compete with Arm in the interconnect IP market, we believe our solutions are complementary to Arm’s processor portfolio and protocol deployment and are actively collaborating on joint automotive solutions. We often execute the integration of Arm processors in heterogeneous environments, which can accelerate the deployment of Arm processors. While smaller companies are developing interconnect solutions, we believe that our extensive investment in research and development over many years creates a barrier to entry. Developing interconnect IP solutions that are robust, configurable, and capable of handling multiple functionalities requires deep technology expertise and large research and development investments. We compete based on die area reduction, lower idle power consumption, improved data movement performance such as frequency, latency, and bandwidth, as well as faster time to market. We believe we compete favorably with respect to these factors.

Based on management’s experience, we believe that in order to develop a new interconnect IP product, it would take a new entrant in the interconnect IP market three to four years to develop a mature product, two to four years of market development and five to seven years to build a royalty generating customer base.

Our SIA solutions similarly compete mainly against internally developed solutions. Commercial competitors consist of smaller companies that generally provide point products rather than complete solutions.

Intellectual Property and Proprietary Rights

We rely on a combination of intellectual property rights, including patents, trade secrets, copyrights and trademarks, and contractual protections, to protect our core technology and intellectual property. As of December 31, 2023, we had 154 total allowed or issued patents, pending patent applications and non-expired provisional patent applications worldwide. Of these, we had 73 allowed or issued patents, 64 are U.S. allowed or issued patents, five are allowed or issued China patents, two are South Korea issued patents, one is a U.K. issued patent, and one is a Japan issued patent. The 73 allowed or issued patents generally expire between July 2035 and December 2041. As of December 31, 2023, we had 81 pending non-provisional and provisional patent application filings, 36 in the United States, 21 in Europe, 16 in China, five in South Korea and three in Japan. In addition, we have a trademark program covering, where feasible and in accordance with local laws, our products as well as our corporate names and logos.

Our progress in developing our technology and products, and our ability to compete worldwide, is a direct result of our commitment to develop and maintain leadership of our proprietary products and to develop and file to protect our intellectual property. We rely on a combination of patent, trademark, trade secret, and copyright laws, as well as contractual and licensing restrictions to protect the proprietary aspects of our technology. We also take steps to protect against misuse of our licensed products, for example with license keys that limit the time allowed for our licensee customers to use configuration tools to generate hardware description source code that is used in their semiconductor hardware products.

We routinely use non-disclosure agreements, limited evaluation agreements, and substantive license agreements with procedures to assist customer usage while limiting wrongful disclosure or misuse of our intellectual property. In addition, we are committed to developing products not only in the U.S. but in France and other countries, where the country of origin may favorably impact the ability to license our IP solutions and technology in accordance with applicable export laws and regulations. Technological change and customer needs for emerging feature needs in our solutions inspire and motivate our personnel to update and enhance our offerings periodically.

We focus on patent protection beyond the United States in countries and jurisdictions where we determine that such filings will assist the strategic reach and value of our patent portfolio. Patents and other legal IP protections arise when we have conceived or developed novel and valuable new or improved technology relating to our IP solutions, that may affect our customer and our own licensing business outside the U.S. Certain countries in which our IP solutions are or may be developed, manufactured or sold may not have or enforce laws that protect our technology and intellectual property rights to the same extent as under U.S. law.

Material Agreements

Qualcomm Agreements

In connection with an Asset Purchase Agreement by and among Qualcomm Technologies, Inc. and Qualcomm France SARL (collectively, Qualcomm) and us and certain of our subsidiaries dated as of October 9, 2013, pursuant to which we sold to Qualcomm certain assets and intellectual property related to our FlexNoC product (the Purchase Agreement), we and our affiliates retained a non-exclusive, worldwide, perpetual right under patents acquired under the Purchase Agreement to, among other things, manufacture, license and distribute certain FlexNoC products and certain modifications thereto (the Retained Rights). In addition, we and Qualcomm Technologies, Inc. entered into a License Agreement dated October 11, 2013 (the License Agreement) pursuant to which we and our affiliates obtained a license to, among other things, reproduce, use, license, and distribute certain FlexNoC-related works of authorship and technology that were acquired or owned by Qualcomm in connection with the Purchase Agreement for the purpose of enabling us to continue to offer and support FlexNoC products and certain modifications thereto (the Licensed Rights). There is no charge under the Purchase Agreement for our use of the Retained Rights or the Licensed Rights. Our rights in the Retained Rights continue until the last to expire of the relevant patents, and the License Agreement continues in perpetuity, in each case unless terminated as described below.

Qualcomm may terminate the Retained Rights in the event (i) we or our subsidiaries that are party to the Purchase Agreement breach any material terms of the Purchase Agreement applicable to the Retained Rights or any material terms of the License Agreement and fail to cure any such breach within 90 days after notice of such breach from Qualcomm, or (ii) we or any of our affiliates initiate a claim of patent infringement against Qualcomm or its affiliates (excluding such claims that are counterclaims in proceedings initiated by Qualcomm or its affiliates) and does not withdraw such claim within 30 days after Qualcomm’s written request to do so. Qualcomm may terminate the License Agreement in the event we breach any material terms of the License Agreement or any material terms of the Purchase Agreement applicable to the Retained Rights and fail to cure such breach within 90 days after notice of such breach from Qualcomm. Qualcomm may also terminate rights granted under the License Agreement to a certain development environment used in connection with our FlexNoC product (which could effectively preclude us from continuing to enhance our FlexNoC product and adversely affect our FlexNoC business) in the event of a change of control of our company (as defined in the License Agreement) which would effectively include, in a transaction or series of related transactions, a sale of our company, or the sales of securities by us or our stockholders that would result in the stockholders and option holders of our company as of the date of the License Agreement not retaining beneficial ownership of more than 50% of our company. We believe that, as we have and continue to deliver new products since the date of the License Agreement, such as our range of SIA solutions, Ncore cache coherent interconnect, CodaCache last-level cache, and CSRCompiler physical awareness capabilities, the importance to our business and product portfolio of the FlexNoC development environment will decrease over time.

We may not assign the License Agreement without Qualcomm’s written consent (and a change of control of our company shall be considered an assignment for the purposes of such prohibition) except that we may assign the License Agreement to an acquirer of our business that consists of licensing certain FlexNoC products, and we may only assign the Retained Rights to an entity to whom we have assigned the License Agreement.

Governmental Regulation

We are subject to regulation by various governmental agencies in the United States and other jurisdictions in which we operate. These laws and regulations (and the government entities, regulators, and agencies responsible for their enforcement) in the United States cover among other things: radio frequency emission regulatory activities (Federal Communications Commission); anti-trust regulatory activities (Federal Trade Commission and Department of Justice); insider trading, anti-bribery, and anti-corruption (Department of Justice), consumer protection (Federal Trade Commission); import/export regulatory activities (Department of Commerce and Department of Treasury); product safety regulatory activities (Consumer Products Safety Commission); worker safety (Occupational Safety and Health Administration); environmental protection (Environmental Protection Agency and similar state and local agencies); employment matters (Equal Employment Opportunity Commission); and federal and state tax and other regulations by a variety of regulatory authorities in each of the areas in which we conduct business. Our operations are also subject to the U.S. Foreign Corrupt Practices Act of 1977, as amended (the FCPA), the U.S. domestic bribery statute contained in 18 U.S.C. § 201, the U.S. Travel Act, the USA PATRIOT Act, as well as the anti-corruption, anti-bribery, and anti-money laundering laws in the U.S. and other countries where we conduct business.

In addition, certain of our products, including our IP interconnect and other solutions and technology, are subject to U.S. export controls, including the U.S. Department of Commerce’s Export Administration Regulations (EAR) and economic and trade sanctions regulations administered by the U.S. Treasury Department’s Office of Foreign Assets Controls (OFAC). Other products are subject to French export controls. These regulations may limit the export of our products and technology, and the provision of our services outside of the United States and/or France, or may require export authorizations, including by license, a license exception, or other appropriate government authorizations and conditions, including annual or semi-annual reporting. Export control and economic sanctions laws may also include prohibitions on the sale or supply of certain of our products to embargoed or sanctioned countries, regions, governments, persons, and entities. The export and re-export of our products and technology and the provision of services, including by our partners, must comply with these laws, or else we may be adversely affected through reputational harm, government investigations, penalties, and a denial or curtailment of our ability to export our products and technology. In July 2021, we submitted a voluntary self-disclosure (VSD) to the Bureau of Industry and Security (BIS), noting potential violations of the EAR. On April 28, 2022, the Office of Export Enforcement of the U.S. Department of Commerce's Bureau of Industry and Security closed the matter with the issuance of a warning letter. With respect to government authorizations, we have no pending export license requests to BIS or any other government agency, and no export licenses are currently required to export our products from the United States or other countries to countries where we do business.

Complying with export control and sanctions laws may be time-consuming and may result in the delay or loss of sales opportunities. Although we take precautions to prevent our products and technology from being provided in violation of such laws, our products and technology have previously been, and could in the future be, provided inadvertently in violation of such laws, despite the precautions we take. If we are found to be in violation of U.S. sanctions or export control laws, it could result in substantial fines and penalties for us and the individuals working for us. Changes in export or import laws or sanctions policies may adversely impact our operations, delay the introduction and sale of our products in international markets, or, in some cases, prevent the export or import of our products and technology to certain countries, regions, governments, persons, or entities altogether, which could harm our business.

From time to time, we have adopted and will continue to adopt remedial measures in response to government regulation. For example, we have adopted several remedial measures prior to, in connection with and following the initial notification of voluntary self-disclosure we submitted to BIS. These compliance enhancements were developed and implemented in consultation with outside counsel specializing in U.S. trade compliance. These steps have included annual basic export compliance training within our company, updating our written export control policies and procedures, and adopting a revised export compliance manual in 2021. We have provided export awareness training for relevant personnel including in 2023 and 2022. We previously provided our sales employees worldwide with training in basic export compliance. We engaged third-party vendor software to assist us with an ongoing screening of new and existing customers, third-party agents or representatives, suppliers, and other vendors against U.S., France and several other jurisdictions’ prohibited or restricted party lists. We screen all customers against applicable lists of denied or restricted parties, including the Entity List administered by BIS as well as the list of Specially Designated Nationals and Blocked Persons, administered by the Treasury Department’s Office of Foreign Assets Control.

For a discussion of the various risks we face from regulation and compliance matters, see “Risk Factors—Risks Related to Our Business and Industry—We are subject to data protection, privacy and security laws, regulations, standards and other requirements across different markets where we conduct our business. Our actual or perceived failure to comply with such obligations could harm our business,” “Risk Factors—Risks Related to Legal, Regulatory, Accounting and Tax Matters—Our failure to comply with the large body of laws and regulations to which we are subject could materially harm our business,” “Risk Factors—Risks Related to Legal, Regulatory, Accounting and Tax Matters—Our failure to comply with the Foreign Corrupt Practices Act, other applicable anti-corruption and anti-bribery laws, and applicable anti-money laundering laws could subject us to penalties and other adverse consequences,” “Risk Factors—Risks Related to Legal, Regulatory, Accounting and Tax Matters—We are subject to government regulation, including import, export and economic sanctions laws and regulations that may expose us to liability and increase our costs,” “Risk Factors—Risks Related to Legal, Regulatory, Accounting and Tax Matters—We will lose sales if we are unable to obtain government authorization to export certain of our products and services, and we will be subject to legal and regulatory consequences if we do not comply with applicable export control laws and regulations or if such laws and regulations were to change.”

Human Capital Resources

As of December 31, 2023, we had 243 employees as follows:

We consider relations with our employees to be good and have never experienced a work stoppage. None of our employees are either represented by a labor union, although our employees in France are subject to a collective bargaining agreement.

Our human capital resources objectives include, as applicable, identifying, recruiting, retaining, incentivizing and integrating our existing and additional employees. The principal purposes of our equity incentive plans are to attract, retain and motivate selected employees, consultants and directors through the granting of stock-based compensation awards and cash-based performance bonus awards.

Corporation Information

We were incorporated in the State of Delaware in April 2004. Our principal executive offices are located at 900 E. Hamilton Ave. Suite 300 Campbell, CA 95008. Our telephone number is (408) 470-7300, and our website address is www.arteris.com. The information contained on, or that can be accessed through, our website is not incorporated by reference in this report and does not form a part of this report. You should not consider the information contained on our website to be part of this report in deciding whether to purchase shares of our common stock. Our common stock is traded on the Nasdaq Stock Market under the symbol “AIP”.

Available Information

Our website address is www.arteris.com. Information found on, or accessible through, our website is not a part of, and is not incorporated into, this Annual Report on Form 10-K. We file electronically with the SEC our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Exchange Act. We make available on our website at www.arteris.com, free of charge, copies of these reports and other information as soon as reasonably practicable after we electronically file such material with, or furnish it to, the SEC.